Standard cell design technology is widely used in the semiconductor art to make custom ICs, because it reduces the design time of integrated circuits. Standard cells are usually stored in libraries and provide the designer with many more or less complex functions that are necessary for the circuit design. All standard cells have at least two different views, a symbol view and layout view. The symbol is used to draw the actual circuit schematic. The layout view is used to create the real layout. The big advantage of standard cells is the possibility of using standard cell place and route tools. These computerized tools extract the electrical connections between the cells from the schematic and then the placement software places the standard cells automatically. The cells are placed in several rows. After the placement, the router is used to connect all cells according to the schematic. Placement and routing can be modified by specifying certain constraints, e.g. number of rows, a certain ratio between width and height of the layout, etc. Due to the marketing requirements to develop integrated circuits in very short time frames, standard cell design is becoming more and more important. See, for example, the description given in "Speed and Complexity Fuel CMOS ASIC Growth", ASIC & EDA, Jan. 1993, beginning at pg. 24.
Semiconductor vendors that provide to its customers standard cell capability make available a library of designs for active components, such as bipolar and MOS transistors, and passive components, such as resistors and capacitors. The designs generally conform to particular component geometries built in accordance with particular fabrication processes that the vendor can use to make an IC circuit employing components of the library. The whole system is computer controlled. A customer who desires that the IC vendor supply him with particular custom ICs uses software provided by the vendor, based upon the circuit chosen or functions desired, to choose from the library the components desired and then under computer control to provide a layout of the components and their interconnections such that when implemented as an IC will perform the functions desired by the customer. The components are typically laid out in parallel rows in blocks, typically arranged in rows of cells typically of the same height but different widths to accommodate the size of the component needed, and interconnected using the place and route software via routing channels located between the rows. The above is well known in the art and further details are not necessary to understand the invention. The problem solved by the invention is as follows.
Integrated circuits running with high frequencies are a potential source for RFI (Radio Frequency Interference). One measure to reduce RFI is to include on-chip decoupling capacitors in the design. To gain maximum advantage of these decoupling capacitors, they have to be placed close to drivers and flip-flops. Because most of the blocks of a chip are built by using place and route software, manual placement of capacitors is unwanted.